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EnglishIn this paper we propose an innovative A/D architecture with the ability to acquire an input signal according to the recently introduced Compressed Sensing (CS) paradigm. The architecture relies on the hardware blocks already found in traditional successive-approximation-register (SAR) A/D converter, requiring only the addition of a limited number of switches. The capacitive array at the core of the circuit is used both by the SAR conversion algorithm and to realize the linear combination of consecutive signal samples, as required by the CS framework. The lack of additional active blocks allows for a remarkable saving in sampling energy with respect to published solutions. The role of some design parameters is investigated and solutions to ease the circuital implementation are analyzed.
A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities / PAOLINO, CARMINE; Pareschi, F.; Mangia, M.; Rovatti, R.; Setti, G.. - STAMPA. - 2019(2019), pp. 133-136. ((Intervento presentato al convegno 15th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2019 tenutosi a Lausanne (Switzerland) nel July 15-18, 2019.
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| Titolo: | A Practical Architecture for SAR-based ADCs with Embedded Compressed Sensing Capabilities | |
| Autori: | ||
| Data di pubblicazione: | 2019 | |
| Abstract: | In this paper we propose an innovative A/D architecture with the ability to acquire an input sign...al according to the recently introduced Compressed Sensing (CS) paradigm. The architecture relies on the hardware blocks already found in traditional successive-approximation-register (SAR) A/D converter, requiring only the addition of a limited number of switches. The capacitive array at the core of the circuit is used both by the SAR conversion algorithm and to realize the linear combination of consecutive signal samples, as required by the CS framework. The lack of additional active blocks allows for a remarkable saving in sampling energy with respect to published solutions. The role of some design parameters is investigated and solutions to ease the circuital implementation are analyzed. | |
| ISBN: | 978-1-7281-3549-6 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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http://hdl.handle.net/11583/2786315
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