Front-End Integrated Circuits For Readout of Large Area SiPMs at cryogenic temperature

This work describes the architecture and transistorlevel design of CMOS front-end amplifiers for the readout of large area SiPMs at LAr temperature (87K). Two circuit topologies, based on trans-impedance and common-gate input stages, are discussed and compared. Both circuits were designed using a standard CMOS 110nm technology, and the simulation results obtained with the foundry PDK are presented. The circuits use a power rail of +1.25 V and -1.25 V, and a power budget below 100 mW, for a total gain of 58 dB. The target sensor is a 24cm2 SiPM tile developed in the framework of the Darkside Collaboration. Post-layout simulations with a cryogenic SiPM electrical model indicate that a signal-to-noise ratio above 8 and a jitter better than 15 ns should be achieved for a single photoelectron