Nowadays many Integrated Systems embed auxiliary on-chip instruments whose function is to perform test, debug, calibration, configuration, etc. The growing complexity and the increasing number of these instruments have led to new solutions for their access and control, such as the IEEE 1687 standard. The standard introduces an infrastructure composed of scan chains incorporating configurable elements for accessing the instruments in a flexible manner. Such an infrastructure is known as Reconfigurable Scan Network or RSN. Since permanent faults affecting the circuitry can cause malfunction, i.e., inappropriate behaviour, detecting them is of utmost importance. This paper addresses the issue of generating effective sequences for testing the reconfigurable elements within RSNs using evolutionary computation. Test configurations are extracted with automatic test pattern generation (ATPG) and used to guide the evolution. Postprocessing techniques are proposed to improve the evolutionary fittest solution. Results on a standard set of benchmark networks show up to 27% reduced test time with respect to test generation based on RSN exploration

An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests / Cantoro, Riccardo; Damljanovic, Aleksa; SONZA REORDA, Matteo; Squillero, Giovanni. - In: JOURNAL OF CIRCUITS, SYSTEMS, AND COMPUTERS. - ISSN 0218-1266. - ELETTRONICO. - (2019). [10.1142/S0218126619400073]

An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests

Riccardo Cantoro;Aleksa Damljanovic;Matteo Sonza Reorda;Giovanni Squillero
2019

Abstract

Nowadays many Integrated Systems embed auxiliary on-chip instruments whose function is to perform test, debug, calibration, configuration, etc. The growing complexity and the increasing number of these instruments have led to new solutions for their access and control, such as the IEEE 1687 standard. The standard introduces an infrastructure composed of scan chains incorporating configurable elements for accessing the instruments in a flexible manner. Such an infrastructure is known as Reconfigurable Scan Network or RSN. Since permanent faults affecting the circuitry can cause malfunction, i.e., inappropriate behaviour, detecting them is of utmost importance. This paper addresses the issue of generating effective sequences for testing the reconfigurable elements within RSNs using evolutionary computation. Test configurations are extracted with automatic test pattern generation (ATPG) and used to guide the evolution. Postprocessing techniques are proposed to improve the evolutionary fittest solution. Results on a standard set of benchmark networks show up to 27% reduced test time with respect to test generation based on RSN exploration
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2733953
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