MMSE equalization of multi-Gb/s chip-to-chip interconnects with M-PAM signaling affected by manufacturing tolerances

To further increase the communication speed on a chip-to-chip interconnect, more powerful equalization will be needed to reduce the considerable intersymbol interference caused by frequency-dependent attenuation. These interconnects however are prone to manufacturing tolerances, leading to equalization schemes that ideally are adjustable according to each specific realization. In this paper we make use of the minimum mean-square error criterion to obtain novel reduced-complexity equalizers, which have only some parts adjustable and the remaining parts fixed. These equalization schemes are compared with the all-adjustable equalizers in terms of mean square error and symbol error rate, for communication speeds of 20 Gbit/s and 120 Gbit/s. For a microstrip with 10% tolerance on its parameters, we point out that using a fixed pre-equalizer and an adjustable decision-feedback filter gives rise to only a minor symbol error performance degradation (less than about 1.5 dB), both for 2-PAM and 4-PAM signaling at both considered bit rates.