Hybrid on-line self-test strategy for dual-core lockstep processors

Multi-core processors are increasingly becoming popular even in safety-critical applications, and the compliance of such systems with functional safety standards is thus mandatory. The targeted reliability figures are achieved with a combination of different solutions, in particular a largely employed one is named Dual-Core Lockstep (DCLS) configuration. In this paper, a hybrid scheme for the on-line testing of the lockstep logic is proposed, allowing for non-intrusive run-time test of lockstep comparators. The proposed solution leverages test programs developed according to the Software-Based Self-Test (SBST) approach, used in conjunction with a specialized hardware module. The effectiveness of this approach was assessed on a modified version of the OpenRISC 1200 processor, considering stuck-at faults only.