Problems of a Software Test Library for Multicore System-On-Chip

In recent years the complexity of System-On-Chips growth exponentially, mainly due to the ever-increasing demand for more functionalities, even for embedded applications. In order to fulfil such requests, semiconductor vendors introduced in this market multi-core devices to satisfy the more complex software algorithms use to image recognition for implementing the Advanced Driver Assistance Systems. However, despite the gain in terms of performance, the adoption of multi-core devices poses several issues from the test point of view. In particular, it is necessary to evolve the in-field test strategies (commonly used to increase the reliability level of a processor-based system) from the single core to the multi-core case. We present a possible approach for rapidly migrating a Software Test Library (STL), developed according the Software-Based Self-Test (SBST) approach for a single-core processor, to a multi-core processor. The solution proposed use the hardware semaphores in order to control the access to shared resources among different cores. This approach requiring a minimal modification of the test programs, yet without affecting the fault coverage detected by the STL. The hardware semaphores were exploited in order to implement the parallel execution of the programs among different cores, a precalculated scheduler order is need to optimize the total execution time of all STL on all core of the microcontroller.