TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode front-end ASIC developed to readout the new inner tracking detector of the BESIII experiment, carried out at BEPCII in Beijing. The detector is planned to be installed during the 2018 upgrade and features an innovative three-layer triple-CGEM (Cylindrical Gas Electron Multiplier) with analog readout. The ASIC comprises 64 channels, each of which features a dual-branch architecture to extract and digitize the timestamp and charge of the input signal. The time-of-arrival is provided by a set of low-power TDCs, based on analog interpolation techniques, while the charge measurement is obtained either from the time-over-threshold information or the 10-bit digitization of the signal peak amplitude. Fabricated in a 110 nm CMOS technology, the ASIC has been designed to operate with an input capacitance of about 100 pF, an input dynamic range between 1 and 50 fC, a power consumption of 10 mW/channel and a sustained event rate of 60 kHz/channel.

A mixed-signal ASIC for the readout of Gas Electron Multiplier detectors: Design review and characterization results / Cossio, Fabio. - In: 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). - ELETTRONICO. - 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME):(2017), pp. 33-36. ((Intervento presentato al convegno 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2017) tenutosi a Giardini Naxos - Taormina (IT) nel 12 - 15 June 2017 [10.1109/PRIME.2017.7974100].

A mixed-signal ASIC for the readout of Gas Electron Multiplier detectors: Design review and characterization results

COSSIO, FABIO
2017

Abstract

TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode front-end ASIC developed to readout the new inner tracking detector of the BESIII experiment, carried out at BEPCII in Beijing. The detector is planned to be installed during the 2018 upgrade and features an innovative three-layer triple-CGEM (Cylindrical Gas Electron Multiplier) with analog readout. The ASIC comprises 64 channels, each of which features a dual-branch architecture to extract and digitize the timestamp and charge of the input signal. The time-of-arrival is provided by a set of low-power TDCs, based on analog interpolation techniques, while the charge measurement is obtained either from the time-over-threshold information or the 10-bit digitization of the signal peak amplitude. Fabricated in a 110 nm CMOS technology, the ASIC has been designed to operate with an input capacitance of about 100 pF, an input dynamic range between 1 and 50 fC, a power consumption of 10 mW/channel and a sustained event rate of 60 kHz/channel.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2682030
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