With the high flexibility, increasing computing power and lower power consumption, FPGA devices have gained a lot interest in space and avionic applications. Among different types of FPGA devices, Flash-based FPGA is becoming increasingly attractive since their configuration memory is almost immune to Single Event Upset (SEU) induced by energetic particles. However, when applied in such applications, especially long term space missions, the FPGA devices are subject to cumulative ionizing damage, as known as Total Ionizing Dose (TID). The TID may affect the FPGA causing performance degradation and possible eventual permanent damage leading to functional failure. In this paper, we propose a new workflow for analyzing the TID effect on Flash-based FPGA considering the different distributions of TID over the chip and the different impact factors when the configurable logic is programmed to implement different logics in the design. The experimental results show the feasibility of such workflow to be used as assessment tool at early stage of design development.

A new approach for Total Ionizing Dose effect analysis on Flash-based FPGA / Zhang, Qiutao; Azimi, Sarah; LA VACCARA, Germano; Sterpone, Luca; Du, Boyang. - In: MICROELECTRONICS RELIABILITY. - ISSN 0026-2714. - 76-77:(2017), pp. 58-63. [10.1016/j.microrel.2017.07.066]

A new approach for Total Ionizing Dose effect analysis on Flash-based FPGA

AZIMI, SARAH;LA VACCARA, GERMANO;STERPONE, LUCA;DU, BOYANG
2017

Abstract

With the high flexibility, increasing computing power and lower power consumption, FPGA devices have gained a lot interest in space and avionic applications. Among different types of FPGA devices, Flash-based FPGA is becoming increasingly attractive since their configuration memory is almost immune to Single Event Upset (SEU) induced by energetic particles. However, when applied in such applications, especially long term space missions, the FPGA devices are subject to cumulative ionizing damage, as known as Total Ionizing Dose (TID). The TID may affect the FPGA causing performance degradation and possible eventual permanent damage leading to functional failure. In this paper, we propose a new workflow for analyzing the TID effect on Flash-based FPGA considering the different distributions of TID over the chip and the different impact factors when the configurable logic is programmed to implement different logics in the design. The experimental results show the feasibility of such workflow to be used as assessment tool at early stage of design development.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2679571
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