Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data, in particular secret keys used in crypto-processors for encoding information in such a way that only knowledge of the secret key allows to access it. This paper presents a scan attack countermeasure based on the encryption of the scan chain content. The goal is to counteract the security threats and, at the same time, to preserve test efficiency, diagnosis and debugging abilities. We propose to use the secret-key management policy embedded in the device under test in order to encrypt both control and observed data at test time. This solution does not require additional key management, provides same test/diagnostic and debug facilities as under classical scan design with marginal impacts on area and test time.

Scan chain encryption for the test, diagnosis and debug of secure circuits / Da Silva, Mathieu; Flottes, Marie Lise; DI NATALE, Giorgio; Rouzeyre, Bruno; Prinetto, Paolo Ernesto; Restifo, Marco. - ELETTRONICO. - (2017), pp. 1-6. (Intervento presentato al convegno 22nd IEEE European Test Symposium, ETS 2017 tenutosi a cyp nel 2017) [10.1109/ETS.2017.7968248].

Scan chain encryption for the test, diagnosis and debug of secure circuits

DI NATALE, GIORGIO;PRINETTO, Paolo Ernesto;RESTIFO, MARCO
2017

Abstract

Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data, in particular secret keys used in crypto-processors for encoding information in such a way that only knowledge of the secret key allows to access it. This paper presents a scan attack countermeasure based on the encryption of the scan chain content. The goal is to counteract the security threats and, at the same time, to preserve test efficiency, diagnosis and debugging abilities. We propose to use the secret-key management policy embedded in the device under test in order to encrypt both control and observed data at test time. This solution does not require additional key management, provides same test/diagnostic and debug facilities as under classical scan design with marginal impacts on area and test time.
2017
9781509054572
File in questo prodotto:
Non ci sono file associati a questo prodotto.
Pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2678589
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo