The Aethereal network-on-chip and its later variations cover an important role in the on-chip communications field for their capability of ensuring deterministic delivery. This Aethereal feature is offered by the time-driven forwarding operation, which however also introduces possible connection blocking in the system, i.e., a proper time schedule for a given flow cannot be find and hence the communication cannot be established. This paper investigates the blocking problem in the Aethereal network-on-chip, specifically considering a scenario where reservations are performed at run-time. In particular, the paper presents and validates an analytical model to evaluate the blocking probability in the system and proposes a solution to mitigate the problem.
A blocking probability study for the Aethereal network-on-chip / Marchetto, Guido; Tahir, Sarosh; Grosso, Michelangelo. - STAMPA. - (2016), pp. 104-109. (Intervento presentato al convegno IEEE International Design & Test Symposium (IDT) tenutosi a Hammamet, Tunisia nel December 2016) [10.1109/IDT.2016.7843023].
A blocking probability study for the Aethereal network-on-chip
MARCHETTO, GUIDO;TAHIR, SAROSH;GROSSO, MICHELANGELO
2016
Abstract
The Aethereal network-on-chip and its later variations cover an important role in the on-chip communications field for their capability of ensuring deterministic delivery. This Aethereal feature is offered by the time-driven forwarding operation, which however also introduces possible connection blocking in the system, i.e., a proper time schedule for a given flow cannot be find and hence the communication cannot be established. This paper investigates the blocking problem in the Aethereal network-on-chip, specifically considering a scenario where reservations are performed at run-time. In particular, the paper presents and validates an analytical model to evaluate the blocking probability in the system and proposes a solution to mitigate the problem.Pubblicazioni consigliate
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https://hdl.handle.net/11583/2670765
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