Detecting the effects of transient faults is a key point in many processor-based safety-critical applications. This paper proposes to adopt the debug interface module existing today in several processors/controllers available on the market. In this way, we can achieve a good detection capability and small latency with respect to control flow errors, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches and we experimentally evaluated its characteristics demonstrating the advantages and showing the limitations on two pipelined processors. Experimental results performed by fault injection using different software applications demonstrate that the method is able to archieve high fault coverage (more than 95 percent in nearly all the considered cases) with a limited cost in terms of area and performance degradation.

Online Test of Control Flow Errors: A New Debug Interface-Based Approach / Du, Boyang; SONZA REORDA, Matteo; Sterpone, Luca; Luis, Parra; Marta Portela, García; Almudena, Lindoso; Luis, Entrena. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - ELETTRONICO. - 65:6(2016), pp. 1846-1855. [10.1109/TC.2015.2456014]

Online Test of Control Flow Errors: A New Debug Interface-Based Approach

DU, BOYANG;SONZA REORDA, Matteo;STERPONE, LUCA;
2016

Abstract

Detecting the effects of transient faults is a key point in many processor-based safety-critical applications. This paper proposes to adopt the debug interface module existing today in several processors/controllers available on the market. In this way, we can achieve a good detection capability and small latency with respect to control flow errors, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches and we experimentally evaluated its characteristics demonstrating the advantages and showing the limitations on two pipelined processors. Experimental results performed by fault injection using different software applications demonstrate that the method is able to archieve high fault coverage (more than 95 percent in nearly all the considered cases) with a limited cost in terms of area and performance degradation.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2658317
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