Macromodels for simulation-based verification of Systems on Chip and Systems in Package

In recent years the focus on electronic integration shifted from high performance microprocessors, whose integration trend is dictated by the famous Moore law, to System on Chip (SoC) and System in Package (SiP) for mobile and embedded applications. The most common example of SoC can be found in smartphones and tablets: multicore CPU (Central Processing Unit) and GPU (Graphics Processing Unit), memory and Radio Frequency (RF) transceivers are often integrated in the same die or package leading to tremendous reduction in size and power consumption of the device. Therefore SoCs/SiPs are by definition heterogeneous electrical systems, in the sense that analog and digital components for RF and Base Band (BB) applications are closely tied together. To blend such a variety of components in the same electronic package engineers face new difficulties both in design and verification phases. Signal and Power integrity need to be carefully addressed in conjunction with noise levels to address devices constraints. In the context of Analog Mixed Signal (AMS) validation, analog blocks are still the simulation time bottlenecks. The main issues are: the huge complexity of the parasitic networks extracted from components layouts and interconnects, the need of parametric models for non-linear components for what-if analyses, the need of reduced order models for devices having huge ports count like Power Delivery Networks (PDNs) and packages and the lack of low complexity noise complaint synthesis methods for linear macromodels. Although tremendous steps forward were achieved in the last decades in the areas of system identification and model order reduction there are still chances for improvement. In this thesis the state of the art from system identification of Linear Time Invariant (LTI) systems is revised and improved tailoring the needs of AMS simulations for SoC/SiP applications: a new system identification algorithm to cope with linear components having huge dynamical order and ports count (more than two order of magnitudes) is proposed and passivity constraints are verified and imposed by means of parallel algorithms. The identification of parametric linear models is extended to parameterized small-signal models for non-linear devices. Finally a low-complexity noise compliant synthesis algorithm is introduced in order to export the macromodels in standard SPICE-based solvers. The main contributions of this work are: reduction of simulation time for the verification of modern SoCs/SiPs, introduction of parameterized small-signal models for non-linear RF components enabling a simplified assessment of different project scenarios supporting the widespread Intellectual Property (IP) reuse pattern, optimization and simplification of the verification flow based on the provision of multi-purpose IP blocks in the form of noise compliant networks. We are facing the rise of a new era for consumer electronic, and time-to-market is a key feature in the development of new products. Therefore the availability of effective Analog Mixed Signal methodologies becomes a sustainable competitive advantage for companies that are willing to lead these new market segments. The novel algorithms proposed in this work were proved to be of practical relevance in that sense. Most part of the material presented in this work is based on a research activity carried out at the Munich site of Intel Mobile Communication. As a consequence the methodologies proposed here, arising from practical needs, were tested on several commercial benchmarks demonstrating the importance of melting research activities with industries requirements.