Test programs for Software-based Self-Test (SBST) can be exploited during the mission phase of microprocessor-based systems to periodically assess hardware integrity. However, several additional constraints must be imposed due to the coexistence of test programs with the mission application. This paper proposes a method for the generation of SBST on-line test programs for embedded RISC processors, systems where the impact of on-line constraints is significant. The proposed strategy exploits an evolutionary optimizer that is able to create a complete test set of programs relying on a new cooperative scheme. Experimental results showed high fault coverage values on two different modules of a MIPS-like processor core. These two case studies demonstrate the effectiveness of the technique and the low human effort required for its implementation.

Automatic Generation of On-Line Test Programs through a Cooperation Scheme / Ciganda, LYL MERCEDES; Gaudesi, Marco; Lutton, E.; SANCHEZ SANCHEZ, EDGAR ERNESTO; Squillero, Giovanni; Tonda, ALBERTO PAOLO. - STAMPA. - (2012), pp. 13-18. ((Intervento presentato al convegno 13th International Workshop on Microprocessor Test and Verification (MTV), 2012 tenutosi a Austin TX, USA nel 10-13 Dec. 2012 [10.1109/MTV.2012.17].

Automatic Generation of On-Line Test Programs through a Cooperation Scheme

CIGANDA, LYL MERCEDES;GAUDESI, MARCO;SANCHEZ SANCHEZ, EDGAR ERNESTO;SQUILLERO, Giovanni;
2012

Abstract

Test programs for Software-based Self-Test (SBST) can be exploited during the mission phase of microprocessor-based systems to periodically assess hardware integrity. However, several additional constraints must be imposed due to the coexistence of test programs with the mission application. This paper proposes a method for the generation of SBST on-line test programs for embedded RISC processors, systems where the impact of on-line constraints is significant. The proposed strategy exploits an evolutionary optimizer that is able to create a complete test set of programs relying on a new cooperative scheme. Experimental results showed high fault coverage values on two different modules of a MIPS-like processor core. These two case studies demonstrate the effectiveness of the technique and the low human effort required for its implementation.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2504403
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