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EnglishWe developed a methodology for the design and fabrication of silicon nanowire-based circuits. Starting from a functional description of the circuit and using technological data, we generated the physical design of the described function by placing nanowires, FETs and connections. We modeled each circuit sub-block considering resistances, capacitances and FET currents, taking into account gate quantum capacitance. We extracted a post-layout netlist of the whole circuit, suitable for a detailed spice simulation. As an example, we executed an ELDO simulation for a 2-bit adder demonstrating unprecedented capabilities with respect to the nanoarray related literature. We show our fabrication experiments based on Metal-assisted Etching and we are now ready for devices characterization and models validation.
Silicon nanoarray circuits design, modeling, simulation and fabrication / S.Frache; D.Chiabrando; M. Graziano; E. Enrico; L. Boarino; M. Zamboni. - In: PROCEEDINGS OF THE ... IEEE CONFERENCE ON NANOTECHNOLOGY. - ISSN 1944-9399. - STAMPA. - 1(2012), pp. 1-5. ((Intervento presentato al convegno IEEE International conference on Nanotechnology (IEEE-NANO) tenutosi a Birmingham, UK nel 20-23 August [10.1109/NANO.2012.6322083].
| Titolo: | Silicon nanoarray circuits design, modeling, simulation and fabrication | |
| Autori: | ||
| Data di pubblicazione: | 2012 | |
| Rivista: | ||
| Abstract: | We developed a methodology for the design and fabrication of silicon nanowire-based circuits. Sta...rting from a functional description of the circuit and using technological data, we generated the physical design of the described function by placing nanowires, FETs and connections. We modeled each circuit sub-block considering resistances, capacitances and FET currents, taking into account gate quantum capacitance. We extracted a post-layout netlist of the whole circuit, suitable for a detailed spice simulation. As an example, we executed an ELDO simulation for a 2-bit adder demonstrating unprecedented capabilities with respect to the nanoarray related literature. We show our fabrication experiments based on Metal-assisted Etching and we are now ready for devices characterization and models validation. | |
| ISBN: | 9781467321983 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| nanoarray-IEEENANO.pdf | 2. Post-print / Author's Accepted Manuscript | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
http://hdl.handle.net/11583/2503208
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