We developed a methodology for the design and fabrication of silicon nanowire-based circuits. Starting from a functional description of the circuit and using technological data, we generated the physical design of the described function by placing nanowires, FETs and connections. We modeled each circuit sub-block considering resistances, capacitances and FET currents, taking into account gate quantum capacitance. We extracted a post-layout netlist of the whole circuit, suitable for a detailed spice simulation. As an example, we executed an ELDO simulation for a 2-bit adder demonstrating unprecedented capabilities with respect to the nanoarray related literature. We show our fabrication experiments based on Metal-assisted Etching and we are now ready for devices characterization and models validation.

Silicon nanoarray circuits design, modeling, simulation and fabrication / Frache, Stefano; Chiabrando, Diego; Graziano, Mariagrazia; Enrico, Emanuele; L., Boarino; Zamboni, Maurizio. - In: PROCEEDINGS OF THE ... IEEE CONFERENCE ON NANOTECHNOLOGY. - ISSN 1944-9399. - STAMPA. - 1:(2012), pp. 1-5. ((Intervento presentato al convegno IEEE International conference on Nanotechnology (IEEE-NANO) tenutosi a Birmingham, UK nel 20-23 August [10.1109/NANO.2012.6322083].

Silicon nanoarray circuits design, modeling, simulation and fabrication

FRACHE, STEFANO;CHIABRANDO, DIEGO;GRAZIANO, MARIAGRAZIA;ENRICO, EMANUELE;ZAMBONI, Maurizio
2012

Abstract

We developed a methodology for the design and fabrication of silicon nanowire-based circuits. Starting from a functional description of the circuit and using technological data, we generated the physical design of the described function by placing nanowires, FETs and connections. We modeled each circuit sub-block considering resistances, capacitances and FET currents, taking into account gate quantum capacitance. We extracted a post-layout netlist of the whole circuit, suitable for a detailed spice simulation. As an example, we executed an ELDO simulation for a 2-bit adder demonstrating unprecedented capabilities with respect to the nanoarray related literature. We show our fabrication experiments based on Metal-assisted Etching and we are now ready for devices characterization and models validation.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2503208
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