Silicon nanoarray circuits design, modeling, simulation and fabrication

We developed a methodology for the design and fabrication of silicon nanowire-based circuits. Starting from a functional description of the circuit and using technological data, we generated the physical design of the described function by placing nanowires, FETs and connections. We modeled each circuit sub-block considering resistances, capacitances and FET currents, taking into account gate quantum capacitance. We extracted a post-layout netlist of the whole circuit, suitable for a detailed spice simulation. As an example, we executed an ELDO simulation for a 2-bit adder demonstrating unprecedented capabilities with respect to the nanoarray related literature. We show our fabrication experiments based on Metal-assisted Etching and we are now ready for devices characterization and models validation.