Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodology based on an evolutionary tool which exploits high level metrics is presented. To strengthen the correlation between high-level coverage and the gate-level fault coverage, in the case of peripheral cores, the FSMs embedded in the system are identified and then dynamically extracted via simulation, while transition coverage is used as a measure of how much the system is exercised. The results obtained by the evolutionary tool outperform those obtained by a skilled engineer on the same benchmark
An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction / Ravotto, Danilo; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, M; Squillero, Giovanni. - 4974:(2008), pp. 214-223. (Intervento presentato al convegno EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog tenutosi a Naples (ITA) nel March 26-28, 2008) [10.1007/978-3-540-78761-7_22].
An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction
RAVOTTO, DANILO;SANCHEZ SANCHEZ, EDGAR ERNESTO;SCHILLACI M;SQUILLERO, Giovanni
2008
Abstract
Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodology based on an evolutionary tool which exploits high level metrics is presented. To strengthen the correlation between high-level coverage and the gate-level fault coverage, in the case of peripheral cores, the FSMs embedded in the system are identified and then dynamically extracted via simulation, while transition coverage is used as a measure of how much the system is exercised. The results obtained by the evolutionary tool outperform those obtained by a skilled engineer on the same benchmarkPubblicazioni consigliate
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https://hdl.handle.net/11583/1877304
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