Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open-source software. When considering maximum performance in terms of throughput, PC-based routers suffer from limitations stemming from the single PC architecture, e.g., limited bus bandwidth, and high memory access latency. To overcome these limitations, in this paper we present a multistage architecture that combines a layer-2 load-balancer front-end and a layer-3 routing back-end, interconnected by standard Ethernet switches. Both the front-end and the back-end are implemented using standard PCs and open- source software. After describing the architecture, evaluation is performed on a lab test-bed, to show its scalability. While the proposed solution allows to increase performance of PC- based routers, it also allows to distribute packet manipulation functionalities, and to automatically recover from component failures.
Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers / Bianco, Andrea; Finochietto, J; Galante, G; Mazzucchi, D; Mellia, Marco; Neri, Fabio. - STAMPA. - (2006). (Intervento presentato al convegno IEEE GLOBECOM 2006 tenutosi a San Francisco, CA, USA nel 27-30 November 2006) [10.1109/GLOCOM.2006.343].
Scalable Layer-2/Layer-3 Multistage Switching Architectures for Software Routers
BIANCO, ANDREA;MELLIA, Marco;NERI, Fabio
2006
Abstract
Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open-source software. When considering maximum performance in terms of throughput, PC-based routers suffer from limitations stemming from the single PC architecture, e.g., limited bus bandwidth, and high memory access latency. To overcome these limitations, in this paper we present a multistage architecture that combines a layer-2 load-balancer front-end and a layer-3 routing back-end, interconnected by standard Ethernet switches. Both the front-end and the back-end are implemented using standard PCs and open- source software. After describing the architecture, evaluation is performed on a lab test-bed, to show its scalability. While the proposed solution allows to increase performance of PC- based routers, it also allows to distribute packet manipulation functionalities, and to automatically recover from component failures.File | Dimensione | Formato | |
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https://hdl.handle.net/11583/1532085
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