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EnglishThis paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our technique is based on automatic insertion of sleep transistors for cutting sub-threshold current when CMOS gates are in stand-by mode. Area and speed overhead caused by sleep transistor insertion are tightly controlled thanks to: (i) a post-layout incremental modification step that inserts sleep transistors in an existing row-based layout; (ii) an innovative algorithm that selects the subset of cells that can be gated for maximal leakage power reduction, while meeting user-provided constraints on area and delay increase. The presented technique is highly effective and fully compatible with industrial back-end flows, as demonstrated by post-layout analysts on several benchmarks placed and routed with state-of-the art commercial tools for physical design.
Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion / BABIGHIAN P; BENINI L; MACII A.; MACII E. - (2004), pp. 138-143. ((Intervento presentato al convegno ISLPED '04: International Symposium on Low Power Electronics and Design, 2004. tenutosi a San Diego, California nel Agosto 2004.
| Titolo: | Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion |
| Autori: | |
| Data di pubblicazione: | 2004 |
| Abstract: | This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. O...ur technique is based on automatic insertion of sleep transistors for cutting sub-threshold current when CMOS gates are in stand-by mode. Area and speed overhead caused by sleep transistor insertion are tightly controlled thanks to: (i) a post-layout incremental modification step that inserts sleep transistors in an existing row-based layout; (ii) an innovative algorithm that selects the subset of cells that can be gated for maximal leakage power reduction, while meeting user-provided constraints on area and delay increase. The presented technique is highly effective and fully compatible with industrial back-end flows, as demonstrated by post-layout analysts on several benchmarks placed and routed with state-of-the art commercial tools for physical design. |
| ISBN: | 1581139292 |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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