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MERODIO CODINACHS, DAVID
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A Novel Error Rate Estimation Approach for UltraScale+ SRAM-based FPGAs
2018 Sterpone, Luca; Azimi, Sarah; Bozzoli, Ludovica; Du, Boyang; Lange, Thomas; Maximilien, Glorieux; Dan, Alexandrescu; Cesar Boatella, Polo; MERODIO CODINACHS, David
SETA: A CAD tool for Single Event Transient Analysis and Mitigation on Flash-based FPGAs
2018 Azimi, Sarah; Du, Boyang; Sterpone, Luca; MERODIO CODINACHS, David; Cattaneo, Luca
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| A Novel Error Rate Estimation Approach for UltraScale+ SRAM-based FPGAs / Sterpone, Luca; Azimi, Sarah; Bozzoli, Ludovica; Du, Boyang; Lange, Thomas; Maximilien, Glorieux; Dan, Alexandrescu; Cesar Boatella, Polo; MERODIO CODINACHS, David. - (2018), pp. 120-126. (Intervento presentato al convegno IEEE Adaptive Hardware and Systems (AHS), 2018 NASA/ESA Conference) [10.1109/AHS.2018.8541474]. | 1-gen-2018 | STERPONE, LUCAAZIMI, SARAHBOZZOLI, LUDOVICADU, BOYANGLANGE, THOMASMERODIO CODINACHS, DAVID + | AHS2019.pdf |
| SETA: A CAD tool for Single Event Transient Analysis and Mitigation on Flash-based FPGAs / Azimi, Sarah; Du, Boyang; Sterpone, Luca; MERODIO CODINACHS, David; Cattaneo, Luca. - ELETTRONICO. - (2018), pp. 49-52. (Intervento presentato al convegno 15th IEEE International Conference on Synthesis, modeling, analysis and Simulation methods and applications to circuit design tenutosi a Prague, Czech Republic nel 2 July- 5 July 2018) [10.1109/SMACD.2018.8434897]. | 1-gen-2018 | Sarah AzimiBoyang DuLuca SterponeDavid Merodio CodinachsCATTANEO, LUCA | SMACD2018_CAMERAREADY.pdf; SETA_A_CAD_Tool_for_Single_Event_Transient_Analysis_and_Mitigation_on_Flash-Based_FPGAs.pdf |