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Citazione Data di pubblicazione Autori File
NBTI effects on tree-like clock distribution networks / Wei, L.; Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2012), pp. 279-282. ((Intervento presentato al convegno GLSVLSI-12: IEEE/ACM Great Lakes symposium on VLSI tenutosi a Salt Lake City, Utah nel May 2012 [10.1145/2206781.2206849]. 1-gen-2012 MIRYALA, SANDEEPTENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO + -
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation / Tenace, Valerio; Miryala, Sandeep; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2012), pp. 1-6. ((Intervento presentato al convegno THERMINIC-12: IEEE International Workshop on Thermal Investigations of ICs and Systems tenutosi a Budapest nel September. 1-gen-2012 TENACE, VALERIOMIRYALA, SANDEEPCALIMERA, ANDREAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO -
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation / Tenace, Valerio; Miryala, Sandeep; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - In: MICROELECTRONICS JOURNAL. - ISSN 0959-8324. - 45:5(2014), pp. 530-538. [10.1016/j.mejo.2013.11.013] 1-gen-2014 TENACE, VALERIOMIRYALA, SANDEEPCALIMERA, ANDREAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO -
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits / Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2014), pp. 1-4. ((Intervento presentato al convegno PRIME-14: IEEE Conference on Ph.D. Research in Microelectronics and Electronics. 1-gen-2014 TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO -
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits / Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2014). ((Intervento presentato al convegno DATE-14: ACM/IEEE Design, Automation and Test in Europe. 1-gen-2014 TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO -
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization / Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo; Amaru', LUCA GAETANO; De Micheli, Giovanni; Gaillardon, Pierre Emmanuel. - ELETTRONICO. - (2015), pp. 39-44. ((Intervento presentato al convegno Great Lakes Symposium on VLSI [10.1145/2742060.2742098]. 1-gen-2015 MIRYALA, SANDEEPTENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMOAMARU', LUCA GAETANO + gls157s-miryala.pdf
Ultra-low power circuits using graphene p-n junctions and adiabatic computing / Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - In: MICROPROCESSORS AND MICROSYSTEMS. - ISSN 0141-9331. - ELETTRONICO. - 39:8(2015), pp. 962-972. [10.1016/j.micpro.2015.05.018] 1-gen-2015 MIRYALA, SANDEEPTENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO main.pdf; 1-s2.0-S0141933115000708-main.pdf
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits / Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - ELETTRONICO. - (2015), pp. 1-6. ((Intervento presentato al convegno 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 tenutosi a usa nel 2015 [10.1145/2744769.2744880]. 1-gen-2015 TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO main.pdf
CAD Tools for Graphene-Based Electronic Circuits / Tenace, Valerio. - (2016). 1-gen-2016 TENACE, VALERIO tenace_thesis.pdf
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits / Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - (2016), pp. 1-6. ((Intervento presentato al convegno 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 tenutosi a Tallin, Estonia nel 26-28 Settembre 2016 [10.1109/VLSI-SoC.2016.7753575]. 1-gen-2016 TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO vlsisoc2016_multi.pdf; 07753575.pdf
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture / Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - ELETTRONICO. - (2016), pp. 145-150. ((Intervento presentato al convegno 26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016 tenutosi a usa nel 2016 [10.1145/2902961.2902970]. 1-gen-2016 TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO main.pdf; 2902961.2902970.pdf
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies / Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - ELETTRONICO. - (2016), pp. 2897-2897. ((Intervento presentato al convegno 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 tenutosi a Montreal's Sheraton Centre, can nel 2016 [10.1109/ISCAS.2016.7539200]. 1-gen-2016 TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO 07539200.pdf
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs / Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - STAMPA. - 63:12(2016), pp. 1111-1115. [10.1109/TCSII.2016.2624145] 1-gen-2016 TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO TCSII2624145.pdf; 07728047.pdf
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits / Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - STAMPA. - 508:(2017), pp. 60-82. [10.1007/978-3-319-67104-8_4] 1-gen-2017 TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO main.pdf
Activation-kernel extraction through machine learning / Tenace, Valerio; Calimera, Andrea. - (2017), pp. 5-8. ((Intervento presentato al convegno 1st New Generation of CAS, NGCAS 2017 tenutosi a ita nel 2017 [10.1109/NGCAS.2017.29]. 1-gen-2017 Tenace, ValerioCalimera, Andrea -
Multiplication by Inference using Classification Trees: A Case-Study Analysis / Rizzo, Roberto Giorgio; Tenace, Valerio; Calimera, Andrea. - (2018), pp. 1-5. ((Intervento presentato al convegno IEEE International Symposium on Circuits and Systems (ISCAS) [10.1109/ISCAS.2018.8351206]. 1-gen-2018 Rizzo, Roberto GiorgioTenace, ValerioCalimera, Andrea -
A compression-driven training framework for embedded deep neural networks / Grimaldi, M.; Pugliese, F.; Tenace, V.; Calimera, A.. - (2018), pp. 45-50. ((Intervento presentato al convegno 2018 Workshop on INTelligent Embedded Systems Architectures and Applications, INTESA 2018 tenutosi a ita nel 2018 [10.1145/3285017.3285021]. 1-gen-2018 Grimaldi M.PUGLIESE, FEDERICOTenace V.Calimera A. -
Quasi-exact logic functions through classification trees / Tenace, Valerio; Calimera, Andrea. - In: INTEGRATION. - ISSN 0167-9260. - 63:(2018), pp. 248-255. [10.1016/j.vlsi.2018.06.007] 1-gen-2018 Tenace, ValerioCalimera, Andrea 1-s2.0-S0167926017307903-main.pdf
Inferential Logic: A Machine Learning Inspired Paradigm for Combinational Circuits / Tenace, V.; Calimera, A.. - 2018-:(2019), pp. 149-154. ((Intervento presentato al convegno 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018 tenutosi a ita nel 2018 [10.1109/VLSI-SoC.2018.8644808]. 1-gen-2019 Tenace V.Calimera A. 08644808.pdf; VLSI-SOC_2018_paper_79.pdf
Layer-wise compressive training for convolutional neural networks / Grimaldi, Matteo; Tenace, Valerio; Calimera, Andrea. - In: FUTURE INTERNET. - ISSN 1999-5903. - 11:1(2019). [10.3390/fi11010007] 1-gen-2019 Grimaldi, MatteoTenace, ValerioCalimera, Andrea futureinternet-11-00007.pdf
Mostrati risultati da 1 a 20 di 21
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