HAMLET: HW/SW Co-Design of an FPGA Accelerator for Leighton–Micali Post-Quantum Signatures in Embedded Systems

The transition to Post-Quantum Cryptography (PQC) introduces substantial computational overhead, particularly for hash-based signature schemes such as Leighton-Micali Signature (LMS), which strain the limited compute, latency, and energy budgets of embedded systems. This paper presents HAMLET, an FPGA-based accelerator for LMS signature generation and verification, integrated with software in a HW/SW co-design on embedded platforms. The proposed architecture targets the dominant bottleneck, namely Winternitz chain evaluation, and exploits chain-level parallelism through a configurable array of SHA-256 cores controlled by a dynamic scheduler. The degree of parallelism is tunable, enabling exploration of performance-area trade-offs under different LMS parameter sets. To enable a fair and system-relevant comparison, the reference LMS implementation is integrated with the accelerator via a Direct Memory Access (DMA)-based Advanced eXtensible Interface (AXI) interface on a PYNQ-Z2 SoC, so that measured latencies include both processing system (PS)-programmable logic (PL) data movement and kernel execution. A system-level evaluation shows that the proposed co-design reduces the LMS Winternitz-chain and Kc kernel latency by up to 26×, and the corresponding kernel-plus-DMA execution time by close to an order of magnitude, compared to a software-only baseline. Shorter execution times also translate into substantial energy savings per signature, confirming the viability of Field-Programmable Gate Array (FPGA)-based acceleration for practical LMS deployment in embedded Post-Quantum (PQ) cryptographic systems.