SNN2MCU: deploying Spiking Neural Networks on commercial microcontrollers using the Neuromorphic Intermediate Representation

Spiking Neural Networks (SNNs) represent a significant advancement in machine learning, enabling efficient computation inspired by biological neural dynamics and making them suitable for power- and resource-constrained Artificial Intelligence of Things (AIoT) applications. However, their full potential is typically achieved only on neuromorphic hardware, which remains costly and not widely accessible. In this paper, we propose a strategy for running SNNs on non-dedicated devices. Our method relies on the SNN2MCU framework, which enables their execution on widely available, low-power microcontroller units (MCUs). The low-latency execution of such networks on ARM and RISC-V architectures is facilitated by a C library that employs techniques such as fixed-point arithmetic with reduced bit-depth, DSP vectorized functions, and multi-level memory layouts. Moreover, the development of an automated parser that is compatible with the neuromorphic Intermediate Representation (NIR) facilitates the seamless conversion of high-level SNN models into efficient embedded code. Two real-world use case scenarios, executed on STM32H7 and GAP8 platforms, demonstrate the capability of microcontrollers to support SNN-based AIoT applications, achieving real-time inference, accuracy comparable to desktop simulators, and competitive power consumption.