The paper presents an active gate driver implementing two approaches for mitigating the over (under) voltages caused by the fast switching of WBG power transistors. The first is based on the fact that the overshoot (undershoot) and the oscillations following the turn on (off) of a power transistor deal with the switching speed. This can be limited acting on the magnitude of the gate current sourced (sunk) to (from) the gate terminal. A gate driver having the output transistors partitioned in elementary ones, each one driven independently from the others, so that the current sourced (sunk) to (from) the power transistor gate terminal can be set by the user. The second solution proposed in this work is based on the turning off of the gate driver for a short time interval during the Miller plateau. In this case the partitioning of the gate driver output transistors is not needed. A test chip implementing the two solutions was designed, prototyped and experimentally characterized. The effectiveness of the proposed approach is proved by the experimental results.

An Active Gate Driver to Mitigate the Overshoot Due to the Fast Switching of HV E-mode GaN HEMTs / Fiori, F., Nuebling, M., Klotz, F.. - STAMPA. - (2026). (23rd International Conference on IC Design and Technology (ICICDT) 2026 Dresda (Ger) 22-24 June 2026).

An Active Gate Driver to Mitigate the Overshoot Due to the Fast Switching of HV E-mode GaN HEMTs

Fiori, Franco;
2026

Abstract

The paper presents an active gate driver implementing two approaches for mitigating the over (under) voltages caused by the fast switching of WBG power transistors. The first is based on the fact that the overshoot (undershoot) and the oscillations following the turn on (off) of a power transistor deal with the switching speed. This can be limited acting on the magnitude of the gate current sourced (sunk) to (from) the gate terminal. A gate driver having the output transistors partitioned in elementary ones, each one driven independently from the others, so that the current sourced (sunk) to (from) the power transistor gate terminal can be set by the user. The second solution proposed in this work is based on the turning off of the gate driver for a short time interval during the Miller plateau. In this case the partitioning of the gate driver output transistors is not needed. A test chip implementing the two solutions was designed, prototyped and experimentally characterized. The effectiveness of the proposed approach is proved by the experimental results.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/3012478