Parallel Connection Investigation of GaN FET Devices for High-Current Switches

Gallium-Nitride (GaN) FET devices are increasingly becoming significant in power electronics due to their high switching frequency and current density. However, parallel connection of these devices poses challenges in current sharing and peak currents during switching transients. This paper addresses these issues by analyzing key electrical parameters, employing both simulations and experimental validations with a custom PCB prototype. LTSpice simulations and practical testing are carried out to evaluate parameter mismatches, layout management, and gate driver design. The paper aims to give insights into the designing boards with paralleled GaN FETs for high-power converters. Results show that precise control of turn-on delays and optimal layout management minimize losses and ensure balanced current distribution. This paper provides guidelines for optimizing GaN FET performance in parallel connections, with applications in DC-DC converters, DC-AC inverters for motor drive applications and high-performance power systems.