A Novel Tester-Based Approach for Functional Testing of Hardware Timers

This paper proposes a novel multi-site functional testing methodology for hardware timers, essential components in safety-critical systems. The methodology employs a custom flexible tester modified for JTAG-based multi-site testing, enabling simultaneous evaluation of multiple devices under test (DUTs) alongside a golden chip for reference. By varying voltage and frequency conditions, the DUT’s timer behaviour is compared to the golden chip’s to identify faults such as transition delay and small delay faults. Experimental results demonstrate the effectiveness of the methodology in enhancing reliability and ensuring compliance with stringent safety standards like ISO26262 and DO-178C. This approach provides a scalable and adaptable solution for testing complex SoC designs in diverse safety-critical applications.