Predicting Digital Layout Success in Analog-on-Top Designs Using Machine Learning

Designing Analog-On-Top Mixed Signal (AMS) Integrated Circuits (ICs) is a labor-intensive and mainly manual process. A crucial step in this flow is reserving specific areas on the top-level layout to place digital blocks. This requires multiple time-consuming iterations between digital and analog teams, as several design characteristics are to be considered to determine whether the area is sufficient. Existing automated solutions are generally limited, as they often yield limited accuracy or have been tested only on simplistic use cases. In this work, we propose a Machine-Learning (ML) solution to determine whether the reserved area for a digital block is sufficient, handling this task as a supervised classification problem. Specifically, we perform an extensive benchmark of different ML models on labeled production-level designs, obtaining up to 94.8 % F1 score. Finally, we provide an in-depth analysis of how different design features impact the prediction quality of several ML models, showing that a feature reduction technique can improve the final accuracy by up to 8.6 %.