The article presents the design and the architectural optimization of a new Hybrid, High-Resolution Digital Pulse Width Modulator (HHR-DPWM) and its implementation in an integrated, digitally-controlled, voltage-mode, point-of-load (POL) buck converter for automotive applications. The pro-posed HHR-DPWM architecture, which features a synchronous counter-based DPWM, a delay locked loop (DLL)-based digital-to-time converter (DTC) with sub-clock-cycle resolution, and Dyadic Digital Pulse Modulation (DDPM) dithering, is optimized to meet the requirements of the POL converter at low cost and design effort. The POL converter with the proposed HHR-DPWM is fabricated in the 110 nm BCD9s technology by STMi-croelectronics. Based on measurements, the converter regulates the output voltage with 2 mV accuracy, 2 mV peak to peak ripple and a power efficiency up to 95.4% at 3.4 V output voltage.

Design of a Hybrid High Resolution Digital PWM for a Smart Power Point-of-Load Power Converter / Dalal, Neha; Landini, Matteo; Vilmercati, Paolo; Musolino, Francesco; Crovetti, Paolo Stefano. - STAMPA. - (2025), pp. 1-5. (Intervento presentato al convegno 2025 IEEE International Symposium on Circuits and Systems (ISCAS) tenutosi a London (UK) nel 25-28 May 2025) [10.1109/ISCAS56072.2025.11043984].

Design of a Hybrid High Resolution Digital PWM for a Smart Power Point-of-Load Power Converter

Neha Dalal;Francesco Musolino;Paolo Stefano Crovetti
2025

Abstract

The article presents the design and the architectural optimization of a new Hybrid, High-Resolution Digital Pulse Width Modulator (HHR-DPWM) and its implementation in an integrated, digitally-controlled, voltage-mode, point-of-load (POL) buck converter for automotive applications. The pro-posed HHR-DPWM architecture, which features a synchronous counter-based DPWM, a delay locked loop (DLL)-based digital-to-time converter (DTC) with sub-clock-cycle resolution, and Dyadic Digital Pulse Modulation (DDPM) dithering, is optimized to meet the requirements of the POL converter at low cost and design effort. The POL converter with the proposed HHR-DPWM is fabricated in the 110 nm BCD9s technology by STMi-croelectronics. Based on measurements, the converter regulates the output voltage with 2 mV accuracy, 2 mV peak to peak ripple and a power efficiency up to 95.4% at 3.4 V output voltage.
2025
979-8-3503-5684-7
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/3001351