Automating the Use of State-Space Representations in Mixed-Signal IC Design and Verification

This paper proposes a methodology based on the modified nodal analysis (MNA) automating the extraction of symbolic State-Space (STSP) models directly from electrical circuit netlists, uniquely defining outputs within the schematic itself. The high level of automation achieved significantly reduces the modeling effort and enables rapid adaptation to changes in specifications or circuit topology. Furthermore, this paper details the process by which the extracted models can be utilized to generate behavioral components for use within both analog and digital simulation environments. This ensures a consistent design flow throughout the integrated circuit (IC) design process and markedly enhancing workflow efficiency.