Redox-based resistive switching devices can be switched between a high resistance state and a low resistance state in a reversible manner. An important requirement is the stable operation between these two states for a high amount of switching cycles. In this work the switching dynamics of these devices are investigated by means of device simulation. Hereby, we discuss the conditions for which a fading memory effect appears. In this case the switching dynamics of set and reset process needs to be identical. Using sinusoidal input voltages fading memory behavior is observed in the simulation results. The final steady-state oscillation between two resistance states is only determined by the input voltage signal and not by the initial state of the device. Moreover, it is found that the time to reach the steady-state oscillation, the oscillation amplitude and its mean value depend on a device inherent series resistance. This result opens a way for tuning the resulting reliable operation window for memory operation by means of device engineering.

On the Origin of the Fading Memory Effect in ReRAMs / Menzel, S; Waser, R; Siemon, A; La Torre, C; Schulten, M; Ascoli, A; Tetzlaff, R. - ELETTRONICO. - (2017). (Intervento presentato al convegno 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) tenutosi a Thessaloniki (Greece) nel 25-27 September 2017) [10.1109/PATMOS.2017.8106963].

On the Origin of the Fading Memory Effect in ReRAMs

Ascoli A;
2017

Abstract

Redox-based resistive switching devices can be switched between a high resistance state and a low resistance state in a reversible manner. An important requirement is the stable operation between these two states for a high amount of switching cycles. In this work the switching dynamics of these devices are investigated by means of device simulation. Hereby, we discuss the conditions for which a fading memory effect appears. In this case the switching dynamics of set and reset process needs to be identical. Using sinusoidal input voltages fading memory behavior is observed in the simulation results. The final steady-state oscillation between two resistance states is only determined by the input voltage signal and not by the initial state of the device. Moreover, it is found that the time to reach the steady-state oscillation, the oscillation amplitude and its mean value depend on a device inherent series resistance. This result opens a way for tuning the resulting reliable operation window for memory operation by means of device engineering.
2017
978-1-5090-6462-5
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2988488