Modern day optical communications require ever-increasing bandwidths and capacity, in order to keep up with the growth of traffic and resource-intensive applications. This increase in network capacity can be achieved through the use of the residual capacity of current-day infrastructure, although this requires switching and routing devices capable of wide-band operation in multiple transmission windows. In this work, we describe the design principle, architecture, and performance simulation of a photonic integrated circuit (PIC) based multi-band WSS, which is envisioned to operate on the S+C+L windows. While the architecture is scalable to an arbitrary channel and port count, we showcase a 24-channel implementation deployed on the 400ZR standard, providing both the penalty evaluation through DSP simulations, as well as a footprint evaluation based on the components design.

Integrated multi-band WSS: from design to performance evaluation / Tunesi, L; Khan, I; Masood, Mu; Ghillino, E; Carena, A; Curri, V; Bardella, P. - ELETTRONICO. - (2023), pp. 1-4. (Intervento presentato al convegno 2023 International Conference on Photonics in Switching and Computing (PSC) tenutosi a Mantova, Italy nel 26-29 September 2023) [10.1109/PSC57974.2023.10297184].

Integrated multi-band WSS: from design to performance evaluation

Tunesi, L;Khan, I;Masood, MU;Carena, A;Curri, V;Bardella, P
2023

Abstract

Modern day optical communications require ever-increasing bandwidths and capacity, in order to keep up with the growth of traffic and resource-intensive applications. This increase in network capacity can be achieved through the use of the residual capacity of current-day infrastructure, although this requires switching and routing devices capable of wide-band operation in multiple transmission windows. In this work, we describe the design principle, architecture, and performance simulation of a photonic integrated circuit (PIC) based multi-band WSS, which is envisioned to operate on the S+C+L windows. While the architecture is scalable to an arbitrary channel and port count, we showcase a 24-channel implementation deployed on the 400ZR standard, providing both the penalty evaluation through DSP simulations, as well as a footprint evaluation based on the components design.
2023
979-8-3503-2370-2
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2984867