The ARCADIA project at INFN is developing Fully Depleted Monolithic Active Pixel Sensors (FD-MAPS). FD-MAPSs collect the charge mainly by drift, which allows for a faster collection time, and a better time resolution. In this context, a 2 x 2 mm2 pixel array optimized for a time resolution better than 100 ps has been fabricated. The individual collection diode has a size of 50 x 50 µm^2. Eight diodes are grouped together and read out by a dedicated front-end channel composed of a charge sensitive amplifier and a discriminator with self-compensation of the offset. To maximize the uniformity of the electric field the electronics is located at the matrix periphery. The sensor is implemented in a 110 nm CMOS technology with 3.3 V and 1.2 V transistors, and 6 metal layers. The different terms that contribute to the system time resolution have been estimated with electronics computer-aided design (ECAD) tools, and optimized to target a time resolution below 100 ps

A Fully Depleted CMOS Sensor Prototype for HEP Timing Applications / Durando, Stefano. - ELETTRONICO. - (2022). (Intervento presentato al convegno 2022 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room Temperature Semiconductor Detector Conference tenutosi a Milano (Italy) nel 05-12 November 2022) [10.1109/NSS/MIC44845.2022.10398961].

A Fully Depleted CMOS Sensor Prototype for HEP Timing Applications

Durando, Stefano
2022

Abstract

The ARCADIA project at INFN is developing Fully Depleted Monolithic Active Pixel Sensors (FD-MAPS). FD-MAPSs collect the charge mainly by drift, which allows for a faster collection time, and a better time resolution. In this context, a 2 x 2 mm2 pixel array optimized for a time resolution better than 100 ps has been fabricated. The individual collection diode has a size of 50 x 50 µm^2. Eight diodes are grouped together and read out by a dedicated front-end channel composed of a charge sensitive amplifier and a discriminator with self-compensation of the offset. To maximize the uniformity of the electric field the electronics is located at the matrix periphery. The sensor is implemented in a 110 nm CMOS technology with 3.3 V and 1.2 V transistors, and 6 metal layers. The different terms that contribute to the system time resolution have been estimated with electronics computer-aided design (ECAD) tools, and optimized to target a time resolution below 100 ps
2022
978-1-6654-8872-3
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2982794