Design of a 1st-order Continuous-Time modulator with a Digital-Based Floating-Inverter Integrator

This paper proposes the design and simulation of an ultra-low-power (ULP) digital-based 1st-order continuous-time Sigma-Delta (CT-SD) modulator for Internet of Things (IoT) applications. Simulation results in a 180-nm standard CMOS technology, demonstrating that the overall modulator consumes only 47 nW, which is considerably low compared to the state-of-the-art. The CT-SD modulator, operating at a supply voltage of 0.4 V and at a 500Hz bandwidth, achieves a spurious-free dynamic range (SFDR) of 54 dB and a signal-to-noiseand-distortion ratio (SNDR) of 47.41 dB, corresponding to an effective number of bits (ENOB) of 7.6 bits and to a Schreier Figure-of-Merit (FOMS) of 147.678-dB. To the best of the author's knowledge, the overall results do not showcase a significant improvement in the field of CT- SD ADCs. Nonetheless, it is crucial to emphasize that we are at the forefront of pioneering a new approach, and these results stand as the current best achievements.