Capacitance-to-digital converter in dual-mode logic: power consumption vs conversion time trade-off

This paper deals with the trade-off between conversion time and power in nW-power capacitance-to-digital converters (CDCs). The CDC used in this work operates at nW power and low voltage down to 0.3 V without the need for any additional circuitry, references, or voltage regulation. It is built on swappable oscillators and takes advantage of the delay-power flexibility of dual-mode logic. Its self-calibration corrects PVT changes and mismatches at any point in the chip lifecycle, doing away with the necessity for cutting during testing. A CDC's test chip in 180nm demonstrates that its power consumption can be dynamically modified from 1.37 nW down to 418 pW at a conversion time down to hundreds of ms, making it suited for harvesting systems with a very tight power budget and changing power sources.