In this paper the behavior analysis of parallel connection of IGBTs under short circuit conditions is presented. The issues of hard switching fault (HSF) and fault under load (FUL) short circuit types are faced by taking into account for the influence of the layout and gate driving parameters. The role of the temperature has been considered too in order to investigate how this quantity affects the IGBTs short circuit phenomenon. An analytical description of the FUL transient is introduced to put in correlation the current and voltage peaks, which are suffered by the IGBT, to the circuit and device parameters. Indeed, the current peak imbalance appearing in a FUL condition is depending on the power layout, on the gate driving conditions and spread on device parameters.

Parallel strings of IGBTs in short circuit transients: Analysis of the parameter influence and experimental behavior / Musumeci, S.; Pagano, R.; Raciti, A.; Frisina, F.; Melito, M.. - ELETTRONICO. - 1:(2002), pp. 555-560. (Intervento presentato al convegno IEEE 2002 28th Annual Conference of the Industrial Electronics Society. IECON 02 tenutosi a Seville, Spain nel 05-08 November 2002) [10.1109/IECON.2002.1187568].

Parallel strings of IGBTs in short circuit transients: Analysis of the parameter influence and experimental behavior

S. Musumeci;
2002

Abstract

In this paper the behavior analysis of parallel connection of IGBTs under short circuit conditions is presented. The issues of hard switching fault (HSF) and fault under load (FUL) short circuit types are faced by taking into account for the influence of the layout and gate driving parameters. The role of the temperature has been considered too in order to investigate how this quantity affects the IGBTs short circuit phenomenon. An analytical description of the FUL transient is introduced to put in correlation the current and voltage peaks, which are suffered by the IGBT, to the circuit and device parameters. Indeed, the current peak imbalance appearing in a FUL condition is depending on the power layout, on the gate driving conditions and spread on device parameters.
2002
0-7803-7474-6
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2980025