We have demonstrated the millimeter-scale fabrication of monolayer epitaxial graphene p−n junction devices using simple ultraviolet photolithography, thereby significantly reducing device processing time compared to that of electron beam lithography typically used for obtaining sharp junctions. This work presents measurements yielding nonconventional, fractional multiples of the typical quantized Hall resistance at ν=2 (RH≈12906Ω) that take the form: (a/b)RH. Here, a and b have been observed to take on values such 1, 2, 3, and 5 to form various coefficients of RH. Additionally, we provide a framework for exploring future device configurations using the LTspice circuit simulator as a guide to understand the abundance of available fractions one may be able to measure. These results support the potential for drastically simplifying device processing time and may be used for many other two-dimensional materials.
Nonconventional Quantized Hall Resistances Obtained with ν = 2 Equilibration in Epitaxial Graphene p-n Junctions / Rigosi, Albert F.; Patel, Dinesh; Marzano, Martina; Kruskopf, Mattias; Hill, Heather M.; Jin, Hanbyul; Hu, Jiuning; Walker, Angela R. Hight; Ortolano, Massimo; Callegaro, Luca; Chi-Te, Liang; Newell, David B.. - ELETTRONICO. - (2022), pp. 1-37. [10.48550/arXiv.2201.09791]
Nonconventional Quantized Hall Resistances Obtained with ν = 2 Equilibration in Epitaxial Graphene p-n Junctions
Ortolano, Massimo;
2022
Abstract
We have demonstrated the millimeter-scale fabrication of monolayer epitaxial graphene p−n junction devices using simple ultraviolet photolithography, thereby significantly reducing device processing time compared to that of electron beam lithography typically used for obtaining sharp junctions. This work presents measurements yielding nonconventional, fractional multiples of the typical quantized Hall resistance at ν=2 (RH≈12906Ω) that take the form: (a/b)RH. Here, a and b have been observed to take on values such 1, 2, 3, and 5 to form various coefficients of RH. Additionally, we provide a framework for exploring future device configurations using the LTspice circuit simulator as a guide to understand the abundance of available fractions one may be able to measure. These results support the potential for drastically simplifying device processing time and may be used for many other two-dimensional materials.File | Dimensione | Formato | |
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Rigosi2022_arXiv_2201_09791.pdf
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https://hdl.handle.net/11583/2979005