Archivio Istituzionale della RicercaWe automatically maximize fault-tolerance in nanoarrays based on silicon nanowires and Gate-All-Around transistors optimizing their topology vs. several distributions of faults inherited by technology. We added a Monte Carlo engine in our nanoarchitecture design tool ToPoliNano and verified the effectiveness of the fault-tolerance algorithm over several circuits and faults distributions.
Fault tolerant nanoarray circuits: Automatic design and verification / Ranone, P.; Turvani, G.; Riente, F.; Graziano, M.; Roch, M. R.; Zamboni, M.. - ELETTRONICO. - (2014), pp. 1-6. (Intervento presentato al convegno VLSI Test Symposium tenutosi a Napa (CA) nel 13-17 April 2014) [10.1109/VTS.2014.6818761].
Fault tolerant nanoarray circuits: Automatic design and verification
Turvani, G.;Riente, F.;Graziano, M.;Roch, M. R.;Zamboni, M.
2014
Abstract
We automatically maximize fault-tolerance in nanoarrays based on silicon nanowires and Gate-All-Around transistors optimizing their topology vs. several distributions of faults inherited by technology. We added a Monte Carlo engine in our nanoarchitecture design tool ToPoliNano and verified the effectiveness of the fault-tolerance algorithm over several circuits and faults distributions.
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Fault_tolerant_nanoarray_circuits_Automatic_design_and_verification.pdf
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VTS-2014-faults-nanoarray.pdf
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https://hdl.handle.net/11583/2973101