A Low-Power, Short Dead-Time ASIC for SiPMs Readout with 200 MS/s Sampling Rate

The design of a low-power, 64-channels front-end ASIC for Silicon Photomultipliers is presented. The chip is being developed in a 65 nm CMOS technology and it is optimised for space applications. In each channel, the current pulse delivered by the sensor is amplified, converted into a voltage and sampled at 200 MS/s by an array of 256 cells, each containing a storage capacitor and a single-slope ADC. If a trigger signal is received, the analog samples are digitised in parallel and sent off-chip, otherwise the memory cells are overwritten. The ADC resolution can be programmed in the 7-12 bit range, trading-off dead time with amplitude resolution. The target power consumption is 5 mW/channel. The chip can thus take snapshots of relatively rare events at high sampling rate with low power. The analog memory can be partitioned in shorter slots that work in a time-interleaved configuration. In this way, the input data stream, which usually follows a Poisson distribution, can be derandomized. The chip is scheduled to be submitted for fabrication in the second quarter of 2022. In the paper, the design concept is presented and the ongoing verifications are discussed.