Efficiency modeling of wireless power transfer ASICs accounting for layout parasitics

This paper presents a power-loss model for Lateral- Diffused MOSFETs (LDMOSs) in application-specific integrated circuits (ASICs) in the field of wireless power-transfer system applications. Both the transmitter and receiver power-stages integrated in their respective ASIC units were considered, and the total system efficiency was subsequently estimated. Layout parasitics pertaining to the primary and secondary integrated circuits (ICs) have been considered due to their impact on the total system efficiency, and a charge-sheet control model for the LDMOSs of the three power stages has been developed. Thermal effects induced by heating within the two ASICs were also included, as they exert a significant influence on the amount of both conduction and switching losses. Model results and experimental data are compared and show a satisfactory agreement.