A 28-nm CMOS pixel read-out ASIC for real-time tracking with time resolution below 20 ps

We present the development of a test ASIC, named Timespot1, designed in CMOS 28-nm technology, featuring a 32x32 pixel matrix and a pitch of 55 μm, The ASIC is conceived as the first prototype in a series, capable to read-out pixels with timing capabilities in the range of 30 ps and below. Each pixel is endowed with a charge amplifier, a discriminator and a Time-to-Digital-Converter, capable of time resolutions below 20 ps and read-out rates (per pixel) around 3 MHz. The timing performance are obtained respecting a power budget of about 50 μW per pixel, corresponding to a power density of approximately 2 W/cm 2 · This feature makes the Timespot1 approach an interesting solution for vertex detectors of the next generation of colliders, where high space and time resolutions will be mandatory requirements to cope with the huge amount of tracks per event to be detected and processed.