A processor plays an important role in the security of an entire embedded system. There are two reasons for this. One is that a processor is a general-purpose machine, the program of which can be altered for ill-intended purposes. The other factor that adds to the vulnerability of the embedded system is that an embedded processor uses memory addressing for all its instructions and data. This creates a wide-open gateway in and out of a processor by which secure data can be read, unintended data and instructions can be injected in the processor, and the processor can be made to perform unwanted tasks and operations. The remedy we have planned for this is securing the memory gateways and separating them from the rest of the processor architecture. This is to say that we design configurable gateways for instruction and data read and write operations that can be configured to prevent various forms of attacks coming from the processor’s memory. These configurable gateway architectures are applied to a RISC-V architecture that we have implemented at the RT Level. This paper discusses our implementation of RISC-V architecture that we refer to as AFTAB. The paper emphasizes on the memory gateways of this processor and shows its interfaces with the configuration part of the processor and the architecture of the read and write gateways. After a general presentation of security and threads, we show how AFTAB gateways can be designed and configured for certain types of attacks. All works presented in this paper have been described at the RT Level and synthesized. The synthesis results will be presented.

Aftab: a risc-v implementation with configurable gateways for security / Rajabalipanah, Maryam; Sadeghipourrudsari, Mahboobe; Jahanpeima, Zahra; Roascio, Gianluca; Prinetto, Paolo; Navabi, Zainalabedin. - ELETTRONICO. - (2021), pp. 1-6. ((Intervento presentato al convegno 19th IEEE East-West Design & Test Symposium (EWDTS-2021) tenutosi a Batumi, Georgia nel September 10-13, 2021 [10.1109/EWDTS52692.2021.9580979].

Aftab: a risc-v implementation with configurable gateways for security

Sadeghipourrudsari, Mahboobe;Roascio, Gianluca;Prinetto, Paolo;
2021

Abstract

A processor plays an important role in the security of an entire embedded system. There are two reasons for this. One is that a processor is a general-purpose machine, the program of which can be altered for ill-intended purposes. The other factor that adds to the vulnerability of the embedded system is that an embedded processor uses memory addressing for all its instructions and data. This creates a wide-open gateway in and out of a processor by which secure data can be read, unintended data and instructions can be injected in the processor, and the processor can be made to perform unwanted tasks and operations. The remedy we have planned for this is securing the memory gateways and separating them from the rest of the processor architecture. This is to say that we design configurable gateways for instruction and data read and write operations that can be configured to prevent various forms of attacks coming from the processor’s memory. These configurable gateway architectures are applied to a RISC-V architecture that we have implemented at the RT Level. This paper discusses our implementation of RISC-V architecture that we refer to as AFTAB. The paper emphasizes on the memory gateways of this processor and shows its interfaces with the configuration part of the processor and the architecture of the read and write gateways. After a general presentation of security and threads, we show how AFTAB gateways can be designed and configured for certain types of attacks. All works presented in this paper have been described at the RT Level and synthesized. The synthesis results will be presented.
978-1-6654-4503-0
File in questo prodotto:
File Dimensione Formato  
9580979.pdf

non disponibili

Descrizione: Articolo principale
Tipologia: 2a Post-print versione editoriale / Version of Record
Licenza: Non Pubblico - Accesso privato/ristretto
Dimensione 634.61 kB
Formato Adobe PDF
634.61 kB Adobe PDF   Visualizza/Apri   Richiedi una copia
EWDTS-2021_paper_92.pdf

accesso aperto

Tipologia: 2. Post-print / Author's Accepted Manuscript
Licenza: PUBBLICO - Tutti i diritti riservati
Dimensione 526.74 kB
Formato Adobe PDF
526.74 kB Adobe PDF Visualizza/Apri
Pubblicazioni consigliate

Caricamento pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2923688