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EnglishClock gating is a widely used technique for dynamic power reduction in VLSI design. In its most straightforward application it allows disabling the clock signal of a flip-flop once its state is no longer subject to changes. This paper extends this technique one step further and proposes a systematic way to achieve additional dynamic power savings based on the correlation of flip-flops' activities. Circuits based on shift registers are widely used in digital systems and we selected them to demonstrate the effectiveness of the proposed method. The best, worst and average cases for dynamic power savings tare analyzed. ©2010 IEEE.
Adaptive clock gating for shift register based circuits / Wimer, S.; Koren, I.; Cohen, I.. - (2010), pp. 374-378. ((Intervento presentato al convegno 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010 tenutosi a Eilat, isr nel 2010.
| Titolo: | Adaptive clock gating for shift register based circuits |
| Autori: | |
| Data di pubblicazione: | 2010 |
| Abstract: | Clock gating is a widely used technique for dynamic power reduction in VLSI design. In its most s...traightforward application it allows disabling the clock signal of a flip-flop once its state is no longer subject to changes. This paper extends this technique one step further and proposes a systematic way to achieve additional dynamic power savings based on the correlation of flip-flops' activities. Circuits based on shift registers are widely used in digital systems and we selected them to demonstrate the effectiveness of the proposed method. The best, worst and average cases for dynamic power savings tare analyzed. ©2010 IEEE. |
| ISBN: | 978-1-4244-8681-6 |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| Clk_Gating_in_Shreg.pdf | 2a Post-print versione editoriale / Version of Record | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
http://hdl.handle.net/11583/2873214
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