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EnglishThis work presents the first results on a CMOS analog front-end in 28 nm commercial technology. The proposed scheme was designed to be compatible with future 4D vertex detector requirements for high energy physics experiments, such as: high granularity with a pixel pitch smaller than 100 μm, an average event-rate per unit area of 3 GHzcm-2 [5] and a radiation dose up to 1014 MeV neqcm2. In order to fulfill these system requirements the front-end needs to integrate time measurement capabilities at the pixel level with a resolution better than 100 ps and a power consumption of the order of 10 μW per channel. Analog solutions has been adopted to minimize the effect of per-channel mismatch and process variation on the timing measure with minimal external control. A front-end with an auto zeroed comparator was chosen for this purpose due to its ease of control and low power consumption. A first prototype ASIC has been manufactured and is now under test. In this paper first measurements on its timing performance and offset-compensation capabilities are presented.
First measurements on a discrete-time front-end in 28-nm CMOS technology for timing pixel detectors / Piccolo, L.. - (2019), pp. 1-4. ((Intervento presentato al convegno 2019 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2019 tenutosi a gbr nel 2019.
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| Titolo: | First measurements on a discrete-time front-end in 28-nm CMOS technology for timing pixel detectors | |
| Autori: | ||
| Data di pubblicazione: | 2019 | |
| Abstract: | This work presents the first results on a CMOS analog front-end in 28 nm commercial technology. T...he proposed scheme was designed to be compatible with future 4D vertex detector requirements for high energy physics experiments, such as: high granularity with a pixel pitch smaller than 100 μm, an average event-rate per unit area of 3 GHzcm-2 [5] and a radiation dose up to 1014 MeV neqcm2. In order to fulfill these system requirements the front-end needs to integrate time measurement capabilities at the pixel level with a resolution better than 100 ps and a power consumption of the order of 10 μW per channel. Analog solutions has been adopted to minimize the effect of per-channel mismatch and process variation on the timing measure with minimal external control. A front-end with an auto zeroed comparator was chosen for this purpose due to its ease of control and low power consumption. A first prototype ASIC has been manufactured and is now under test. In this paper first measurements on its timing performance and offset-compensation capabilities are presented. | |
| ISBN: | 978-1-7281-4164-0 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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http://hdl.handle.net/11583/2846513
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