The Dual-Core Lockstep configuration is largely employed in safety-critical System-on-Chips for the sake of compliance with functional safety standards. Such configuration includes two processor cores paired together, always fed with the same identical inputs and their outputs are continuously compared by a set of comparators. However, permanent faults affecting the comparators may invalidate the system functionalities, thus in-field self-test mechanisms are mandatory. In this paper, different in-field self-test solutions are first discussed. Then, a hybrid hardware-software scheme for the on-line testing of the lockstep logic is proposed. Such a solution leverages test programs developed according to the Software-Based Self-Test (SBST) approach, used in conjunction with a specialized hardware module. The effectiveness of this approach was assessed on a modified version of the OpenRISC 1200 processor. Exhaustive experiments demonstrated that it is possible to achieve a fault coverage of stuck-at faults grater than 99%, while at the same time significantly reduce the area overhead of classical approaches.
On-line Self-test Mechanism for Dual-Core Lockstep System-on-Chips / Floridia, Andrea; Sanchez, Ernesto. - In: MICROELECTRONICS RELIABILITY. - ISSN 0026-2714. - ELETTRONICO. - 112C(2020), pp. 1-10.
|Titolo:||On-line Self-test Mechanism for Dual-Core Lockstep System-on-Chips|
|Data di pubblicazione:||2020|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1016/j.microrel.2020.113770|
|Appare nelle tipologie:||1.1 Articolo in rivista|
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