PORTO @ 
Archivio Istituzionale della Ricerca
IRIS è la soluzione IT che facilita la raccolta e la gestione dei dati relativi alle attività e ai prodotti della ricerca. Fornisce a ricercatori, amministratori e valutatori gli strumenti per monitorare i risultati della ricerca, aumentarne la visibilità e allocare in modo efficace le risorse disponibili.
EnglishALCOR is a first prototype of a 32-pixel low-power mixed-signal ASIC developed to readout silicon photomultipliers at low temperature. The chip, designed in 110 nm CMOS technology, performs single photon time-stamping with a maximum event rate of 5 MHz per pixel. The time measurement is performed using low-power TDCs based on analogue time interpolation. The time binning achievable at maximum clock frequency is 50 ps and the target power consumption is less than 5 mW per pixel. Generated data are serialised and transmitted through LVDS drivers. To assert the CMOS electronic behaviour at 77K, a Test Chip has been produced and tested. Results of a digital synchronisation circuit are reported and discussed.
Integrated front-end electronics for single photon time-stamping in cryogenic dark matter detectors / KUGATHASAN, RAMSHAN. - ELETTRONICO. - 15(2020). ((Intervento presentato al convegno LIDINE tenutosi a Manchester (UK) nel 28/08/19 - 30/08/19.
Scheda prodotto non validato
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo
| Titolo: | Integrated front-end electronics for single photon time-stamping in cryogenic dark matter detectors |
| Autori: | |
| Data di pubblicazione: | 2020 |
| Abstract: | ALCOR is a first prototype of a 32-pixel low-power mixed-signal ASIC developed to readout silicon... photomultipliers at low temperature. The chip, designed in 110 nm CMOS technology, performs single photon time-stamping with a maximum event rate of 5 MHz per pixel. The time measurement is performed using low-power TDCs based on analogue time interpolation. The time binning achievable at maximum clock frequency is 50 ps and the target power consumption is less than 5 mW per pixel. Generated data are serialised and transmitted through LVDS drivers. To assert the CMOS electronic behaviour at 77K, a Test Chip has been produced and tested. Results of a digital synchronisation circuit are reported and discussed. |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| LIDINE_JINST_final.pdf | Articolo principale | 1. Preprint / Submitted Version | PUBBLICO - Tutti i diritti riservati | Visibile a tuttiVisualizza/Apri |
| Kugathasan_Integrated.pdf | 2a Post-print versione editoriale / Version of Record | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
http://hdl.handle.net/11583/2805332
Copyright © 2021