Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

The increasing number of embedded instruments used to perform test, monitoring, calibration and debug within a semiconductor device has called for a brand new standard-the IEEE 1687. Such a standard resorts to a reconfigurable scan network to provide efficient and flexible access to instruments and to handle complex structures. As it has to deliver reliable service, many approaches, both formal and simulation-based, have been proposed in the literature to perform test, diagnosis and verification of such networks. This paper focuses on the problem of post-silicon validation of a network, a problem that has not been adequately addressed, yet. We analyze the mismatches between the specification and its silicon implementation, and we propose a methodology to detect a subset of them by applying functional patterns and observing the length of the active scan path. Experimental results on ITC2016 benchmarks demonstrate that the proposed approach is broadly applicable and able to generate very effective sequences. We also classify mismatches that cannot be targeted relying exclusively on the active scan path length information.