We present the design and characterization of TIGER (Turin Integrated Gem Electronics for Readout), a 64-channel ASIC developed for the readout of the CGEM (Cylindrical Gas Electron Multiplier) detector, the proposed inner tracker for the 2018 upgrade of the BESIII experiment, carried out at BEPCII in Beijing. Each ASIC channel features a charge sensitive amplifier coupled to a dual-branch shaper stage, optimized for timing and charge measurement, followed by a mixed-mode back-end that extracts and digitizes the timestamp and charge of the input signals. The time-of-arrival is provided by a set of low-power TDCs, based on analogue interpolation techniques, while the charge measurement is obtained either from the Time-over-Threshold information or with a sample-and-hold circuit. The ASIC has been fabricated in a 110 nm CMOS technology and designed to operate with a 1.2 V power supply, an input capacitance of about 100 pF, an input dynamic range between 3 and 50 fC, a power consumption of about 12 mW/channel and a sustained event rate of 60 kHz/channel. The design and test results of TIGER first prototype are presented showing its full functionality.

Design and performance of the TIGER front-end ASIC for the BESIII Cylindrical Gas Electron Multiplier detector / Cossio, F; Alexeev, M; Bugalho, R; Chai, J; Cheng, W; Rolo, Mdd; Di Francesco, A; Greco, M; Leng, C; Li, H; Maggiora, M; Marcello, S; Mignone, M; Rivetti, A; Varela, J; Wheadon, R. - ELETTRONICO. - (2017). ((Intervento presentato al convegno 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC) tenutosi a Atlanta, GA, USA nel 21-28 Oct. 2017 [10.1109/NSSMIC.2017.8533025].

Design and performance of the TIGER front-end ASIC for the BESIII Cylindrical Gas Electron Multiplier detector

Cossio, F;Chai, J;Cheng, W;Leng, C;
2017

Abstract

We present the design and characterization of TIGER (Turin Integrated Gem Electronics for Readout), a 64-channel ASIC developed for the readout of the CGEM (Cylindrical Gas Electron Multiplier) detector, the proposed inner tracker for the 2018 upgrade of the BESIII experiment, carried out at BEPCII in Beijing. Each ASIC channel features a charge sensitive amplifier coupled to a dual-branch shaper stage, optimized for timing and charge measurement, followed by a mixed-mode back-end that extracts and digitizes the timestamp and charge of the input signals. The time-of-arrival is provided by a set of low-power TDCs, based on analogue interpolation techniques, while the charge measurement is obtained either from the Time-over-Threshold information or with a sample-and-hold circuit. The ASIC has been fabricated in a 110 nm CMOS technology and designed to operate with a 1.2 V power supply, an input capacitance of about 100 pF, an input dynamic range between 3 and 50 fC, a power consumption of about 12 mW/channel and a sustained event rate of 60 kHz/channel. The design and test results of TIGER first prototype are presented showing its full functionality.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2730184
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