A novel region-based pixel digital architecture for latency buffering and trigger matching able to withstand extended trigger latencies and unprecedented data rates at the High-Luminosity LHC upgrade is presented. The architecture features above 99.5% efficiency at nominal 3 GHz/cm 2 pixel hit rate and 1 MHz trigger rate with 12.5 μs trigger latency foreseen at HL-LHC. The overall inefficiency is dominated by dead-time in analogue front-end channels. The digital architecture is organized in pixel regions composed of 4×4 pixels. Charge information is retrieved from each pixel by means of Time-over-Threshold (ToT) using 5-bit counters. A common digital logic shared among pixels stores hits information for the whole trigger latency, handles the local configuration, performs trigger matching and sends zero-suppressed hit data to the chip periphery upon a trigger request. Data compression based on priority queues has been introduced in order to save area and power in the pixel region. The logic has been implemented in a commercial 65 nm CMOS pixel ASIC demonstrator prototyped as part of the Italian INFN CHIPIX65 project. Design specifications, implementation details and simulation results are discussed.

New development on digital architecture for efficient pixel readout ASIC at extreme hit rate for hep detectors at HL-LHC / Paterno, Andrea; Pacher, Luca; Demana, Natale; Rivetti, Angelo; Dellacasa, Giulio; Marconi, Sara; Placidi, Pisana. - ELETTRONICO. - (2016), pp. 1-5. (Intervento presentato al convegno 2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD) tenutosi a Strasbourg, France nel 29 October 2016 - 06 November 2016) [10.1109/NSSMIC.2016.8069855].

New development on digital architecture for efficient pixel readout ASIC at extreme hit rate for hep detectors at HL-LHC

Paterno, Andrea;
2016

Abstract

A novel region-based pixel digital architecture for latency buffering and trigger matching able to withstand extended trigger latencies and unprecedented data rates at the High-Luminosity LHC upgrade is presented. The architecture features above 99.5% efficiency at nominal 3 GHz/cm 2 pixel hit rate and 1 MHz trigger rate with 12.5 μs trigger latency foreseen at HL-LHC. The overall inefficiency is dominated by dead-time in analogue front-end channels. The digital architecture is organized in pixel regions composed of 4×4 pixels. Charge information is retrieved from each pixel by means of Time-over-Threshold (ToT) using 5-bit counters. A common digital logic shared among pixels stores hits information for the whole trigger latency, handles the local configuration, performs trigger matching and sends zero-suppressed hit data to the chip periphery upon a trigger request. Data compression based on priority queues has been introduced in order to save area and power in the pixel region. The logic has been implemented in a commercial 65 nm CMOS pixel ASIC demonstrator prototyped as part of the Italian INFN CHIPIX65 project. Design specifications, implementation details and simulation results are discussed.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2729278
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