MIMO equalization for multi-Gbit/s access nodes affected by manufacturing tolerances

While the requirements for delivering high throughputs increase exponentially with every generation of access node hardware, the device cost is of primary concern. As a result, multiple- input multiple-output (MIMO) equalization, which has been shown to facilitate multi-Gbit/s communication over low-cost parallel electrical interconnects, is emerging as an attractive high- speed interconnect solution for next-generation access nodes. Because of the high operating frequencies, however, the transfer functions of the on- and off-chip interconnects become highly susceptible to manufacturing tolerances (MTs); hence, the equalization filters must be adjusted to the specific channel realization to achieve optimal performance, which involves a high implementation and computational complexity. Considering that the MTs are usually limited, we propose a robust low-complexity transceiver consisting of a fixed MIMO linear pre-equalizer (which avoids the need for feeding back the channel state information to the transmitter), with either a fixed or adjustable MIMO decision- feedback equalizer (DFE). For a specific chip-to- chip interconnect operating at 75 Gbit/s per line and a 26 dB signal-to-noise ratio, we show that the resulting bit error rate does not exceed 10^(-12) for MTs up to 10.5% (fixed DFE) and 17.7% (adjustable DFE) of the nominal line width.