Electrical chip-to-chip interconnects suffer from considerable intersymbol interference at multi-Gb/s data rates, due to the frequency-dependent attenuation. Hence, reliable communication at high data rates requires equalization, to compensate for the channel response. As these interconnects are prone to manufacturing tolerances, the equalizer must be adjusted to each specific channel realization to perform optimally. We adopt a reduced-complexity equalization scheme where (part of) the equalizer is fixed, by involving the channel statistics into the equalizer derivation. For a 10 cm on-board microstrip interconnect with a 10% tolerance on its parameters, we point out that 2-PAM transmission using a fixed prefilter and an adjustable feedback filter, both with few taps, yields only a moderate bit error rate degradation, compared to the all-adjustable equalizer; at a bit error rate of 1e-12 these degradations are about 1.1 dB and 3 dB, when operating at 20 Gb/s and 80 Gb/s, respectively.
Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances / Bailleul, J; Jacobs, L; Manfredi, P; Vande Ginste, D; Moeneclaey, M. - In: COMPUTERS & ELECTRICAL ENGINEERING. - ISSN 0045-7906. - STAMPA. - 62(2017), pp. 17-28.
|Titolo:||Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances|
|Data di pubblicazione:||2017|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1016/j.compeleceng.2017.07.020|
|Appare nelle tipologie:||1.1 Articolo in rivista|