Nanomagnet logic (NML) is a promising technology beyond CMOS technology because it can guarantee an extremely low-power consumption. This technology is extremely different from CMOS in some peculiar aspects: 1) logic gates and wires have the same delay and 2) the layout of a circuit influences its timing characteristics. With these characteristics, it is clear that a simple mapping of CMOS register-transfer level circuits in NML would be inefficient. Circuit logic design must be adapted to this new technology. One interesting aspect is the opportunity to design bit-serial circuits instead of parallel ones and achieve comparable performance with less area occupation. In this paper, we explore the parallel and serial design in NML with magnetoelastic clock through a common case study: the multiply and accumulate algorithm. This is designed in three different versions (fully parallel, fully serial, and parallel–serial) and analyzed in terms of latency, throughput, area occupation, and circuit dissipation.

Parallel and Serial Computation in Nanomagnet Logic: An Overview / Giri, Davide; Causapruno, Giovanni; Riente, Fabrizio. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 26:8(2018), pp. 1427-1437. [10.1109/TVLSI.2018.2821107]

Parallel and Serial Computation in Nanomagnet Logic: An Overview

Causapruno, Giovanni;Riente, Fabrizio
2018

Abstract

Nanomagnet logic (NML) is a promising technology beyond CMOS technology because it can guarantee an extremely low-power consumption. This technology is extremely different from CMOS in some peculiar aspects: 1) logic gates and wires have the same delay and 2) the layout of a circuit influences its timing characteristics. With these characteristics, it is clear that a simple mapping of CMOS register-transfer level circuits in NML would be inefficient. Circuit logic design must be adapted to this new technology. One interesting aspect is the opportunity to design bit-serial circuits instead of parallel ones and achieve comparable performance with less area occupation. In this paper, we explore the parallel and serial design in NML with magnetoelastic clock through a common case study: the multiply and accumulate algorithm. This is designed in three different versions (fully parallel, fully serial, and parallel–serial) and analyzed in terms of latency, throughput, area occupation, and circuit dissipation.
File in questo prodotto:
File Dimensione Formato  
08338338_vlsi-compressed.pdf

non disponibili

Tipologia: 1. Preprint / submitted version [pre- review]
Licenza: Non Pubblico - Accesso privato/ristretto
Dimensione 3.19 MB
Formato Adobe PDF
3.19 MB Adobe PDF   Visualizza/Apri   Richiedi una copia
Pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2713042
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo