Nanomagnet logic (NML) is a promising technology beyond CMOS technology because it can guarantee an extremely low-power consumption. This technology is extremely different from CMOS in some peculiar aspects: 1) logic gates and wires have the same delay and 2) the layout of a circuit influences its timing characteristics. With these characteristics, it is clear that a simple mapping of CMOS register-transfer level circuits in NML would be inefficient. Circuit logic design must be adapted to this new technology. One interesting aspect is the opportunity to design bit-serial circuits instead of parallel ones and achieve comparable performance with less area occupation. In this paper, we explore the parallel and serial design in NML with magnetoelastic clock through a common case study: the multiply and accumulate algorithm. This is designed in three different versions (fully parallel, fully serial, and parallel–serial) and analyzed in terms of latency, throughput, area occupation, and circuit dissipation.
Titolo: | Parallel and Serial Computation in Nanomagnet Logic: An Overview |
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Data di pubblicazione: | 2018 |
Rivista: | |
Digital Object Identifier (DOI): | 10.1109/TVLSI.2018.2821107 |
Appare nelle tipologie: | 1.1 Articolo in rivista |
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http://hdl.handle.net/11583/2713042