Some industrial domains, characterized by particularly strict safety standards – e.g., avionics – are facing issues when addressing the usage of commercial-off-the-shelf multi-processor system-on-chips and in particular new network- on-chip-based architectures. One key issue is related to the usage of such system-on-chips to implement mixed-criticality systems with the main goal of reducing size, weight, and power consumption of on-board equipment by reducing the number of computers moving from federated architectures based on single- core processors to a single multi-core processor. To comply with relevant safety standards, a mixed-criticality system should be proven to enforce isolation among safety-critical and non-safety- critical tasks running on the multi-core hardware platform. This paper presents a software-level methodology tackling such issue. The proposed methodology exploits knowledge of the deterministic routing algorithm used by the network-on-chip to implement a safe and efficient partitioning of the system. This paper presents the software implementation and an experimental evaluation of the solution, proving its suitability for integration in an avionic application.

Efficient Software-Based Partitioning for Commercial-off-the-Shelf NoC-based MPSoCs for Mixed-Criticality Systems / Esposito, Stefano; Avramenko, Serhiy; Violante, Massimo. - ELETTRONICO. - (2018). (Intervento presentato al convegno International Symposium on On-Line Testing and Robust System Design tenutosi a Platja d'Aro (Spain) nel 2-4 July 2018) [10.1109/IOLTS.2018.8474155].

Efficient Software-Based Partitioning for Commercial-off-the-Shelf NoC-based MPSoCs for Mixed-Criticality Systems

Stefano Esposito;Serhiy Avramenko;Massimo Violante
2018

Abstract

Some industrial domains, characterized by particularly strict safety standards – e.g., avionics – are facing issues when addressing the usage of commercial-off-the-shelf multi-processor system-on-chips and in particular new network- on-chip-based architectures. One key issue is related to the usage of such system-on-chips to implement mixed-criticality systems with the main goal of reducing size, weight, and power consumption of on-board equipment by reducing the number of computers moving from federated architectures based on single- core processors to a single multi-core processor. To comply with relevant safety standards, a mixed-criticality system should be proven to enforce isolation among safety-critical and non-safety- critical tasks running on the multi-core hardware platform. This paper presents a software-level methodology tackling such issue. The proposed methodology exploits knowledge of the deterministic routing algorithm used by the network-on-chip to implement a safe and efficient partitioning of the system. This paper presents the software implementation and an experimental evaluation of the solution, proving its suitability for integration in an avionic application.
2018
978-1-5386-5992-2
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2712602
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